A programmable application specific integrated circuit (ASIC) is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a programmable ASIC, the user configures an on-chip interconnect structure of the programmable ASIC so that selected input terminals and selected output terminals of selected on-chip circuit components are electrically connected together in such a way that the resulting circuit is the user-specific circuit desired by the user. In a programmable ASIC employing, for example, amorphous silicon antifuses, selected amorphous silicon antifuses disposed between selected wire segments are xe2x80x9cprogrammedxe2x80x9d to connect the selected wire segments together electrically. Which antifuses are programmed and which antifuses are left unprogrammed determines how the circuit components are interconnected and therefore determines the resulting circuit.
A field programmable gate array (an xe2x80x9cFPGAxe2x80x9d) is one type of programmable application specific integrated circuit. For background information on field programmable gate arrays employing antifuses, see: xe2x80x9cField Programmable Gate Array Technologyxe2x80x9d edited by Stephen Trimberger, 1994, pages 1-14 and 98-170; xe2x80x9cField-Programmable Gate Arraysxe2x80x9d by Stephen Brown et al., 1992, pages 1-43 and 88-202; xe2x80x9cPractical Design Using Programmable Logicxe2x80x9d by David Pellerin and Michael Holley, 1991, pages 84-98; the 1995 QuickLogic Data Book, 1995, pages 1-5 through 2-11 and 6-3 through 6-18; the 1995 Actel FPGA Data Book And Design Guide, 1995, pages ix-xv, 1-5 through 1-34, 1-51 through 1-101, 1-153 through 1-222, 3-1 through 4-56; U.S. Pat. No. 5,424,655 entitled xe2x80x9cProgrammable Application Specific Integrated Circuit Employing Antifuses And Methods Thereforxe2x80x9d; U.S. Pat. No. 5,825,201 entitled xe2x80x9cProgrammable Architecture for a Programmable Integrated Circuit Employing Antifusesxe2x80x9d. The contents of these documents are incorporated herein by reference.
In accordance with the invention, a field programmable gate array includes a serializer/deserializer core for serializing parallel data and deserializing serial data. The serializer/deserializer core includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates.
Data are serialized in a parallel-to-serial circuit which includes a series of registers. Once the parallel data are loaded into the series of registers, they are serially clocked out of the registers by a rising edge signal generated by an stair-step clock generator and provided to the series of registers. Data are deserialized in a serial-to-parallel circuit which includes a series of registers. Serial data are loaded into the registers using a series of rising edge signals generated by the stair-step clock generator. The data are then switched out of the registers onto a parallel bus in a single clock cycle.
The data channel includes a voltage controlled oscillator. The voltage controlled oscillator includes a set of capacitors. A set of transistors couples the capacitors to the output of the voltage controlled oscillator. The gates of the transistors are controlled by a control signal.
A pair of data channels can be tested in a bidirectional loop back test or built in self test. In the loop-back test, the first data channel may be configured to receive data and the second data channel may be configured to transmit data or vice versa. The first data channel receives serial data including an embedded clock, deserializes it, then provides the parallel data and clock to the second data channel. The second data channel reserializes the parallel data, embeds the clock, then transmits the data to be verified. The roles of the data channels are then switched and the loop back test is run in the opposite direction. In a loop back test, the serial data received by the first data channel are provided by an external source and the serial data transmitted by the second data channel are verified by an external test system. In a built in self test, both data channels are coupled to linear feedback shift registers. The linear feedback shift register coupled to the transmitter provides pseudo random parallel data. The linear feedback shift register coupled to the receiver accumulates the parallel data received and generates a signature. If at the end of the data stream the signature matches a predetermined hardwired correct signature, the test is automatically run in the opposite direction with the linear feedback shift registers and data channels switching values. Thus, the first data channel is then reconfigured to transmit data and the second data channel is reconfigured to receive data. The second data channel receives serial data, deserializes it, then provides the parallel data to the first data channel. The first data channel reserializes the parallel data, then transmits the data to be verified.